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Plasma Etching

• Plasma Etching Process in Semiconductor Fabrication
• Plasma Etching Process Chemistry and Chamber Configuration
• Plasma Etching of DRAMS
• Plasma Etching of Microprocessors
• Selective Plasma Etching
• Plasma Etching Development

Plasma Etching Process in Semiconductor Fabrication

Since its introduction in the 1970s, plasma etching has become an integral part of semiconductor integrated circuit (IC) processing. It has become the method of choice for a variety of applications, including fine-line pattern definition, selective processing over topography, planarization, and resist stripping. The complexity of these operations has scaled directly with the dimensions of the products being processed, going from the >1-mu m minimum pattern widths of the early 1980s to the 0.18-mu m (and lower) level of ULSI circuits. Similarly, plasma etching has grown from the use of relatively simple, parallel-plate configurations for a variety of films, to million-dollar modular chambers with multiple frequency generators, electrostatic chucks, externally controlled wall temperatures, and a variety of process control sensors designed specifically for one type of film.

Plasma Etching Process Chemistry and Chamber Configuration

Interactions with resist/film composition, lithographic focus/exposure dose, topography, cleaning technology, and dopant profiles all play key roles in determining appropriate plasma-etching processes. As complexity has increased, these interactions have become more important and more subtle. Meanwhile, the use of more complex chemical systems has evolved as the need for selective, high-aspect-ratio anisotropic features has developed. Simple chlorine- and fluorine-based systems have evolved into multiple-specialty-gas selections independently controlling polymer deposition and etching. To meet these needs, etching (or simply "etch") reactors have evolved that contain highly customized sources, wall materials, pumping configurations, and temperature control facilities.

Plasma Etching of DRAMS

Plasma etching has been used in the fabrication of semiconductor devices ranging from microprocessors to large flat-panel displays. Typically, however, the process is driven by ultrahigh-density structures such as DRAM memory, which requires a low cost per bit.

Dynamic random access memory (DRAM) devices require the use of a wide variety of etching processes. Memory cells are characterized by having a transfer electrode that allows the transmission of charge through a channel to a capacitor which stores and returns charge to external circuitry. This capacitor is typically one of two types: a stacked capacitor, which rests above the transfer gate and contact levels, or a trench capacitor, for which the storage node is etched directly into the substrate.

Plasma Etching of Microprocessors

Logic circuit devices do not require a large capacitor. Instead, they typically place more emphasis on critical dimensions of their gate electrode in order to increase their operating frequency. Because of the complex wiring required on logic-circuit chips, additional levels of metallization are used, placing increased emphasis on "back-end-of-line" (BEOL) oxide and/or metal etching.

Selective Plasma Etching

All of these applications require the transfer of lithographic features to the substrate with minimal critical dimension (CD) loss, or bias. This feature is an important component of device performance, since at certain levels (e.g., at the gate electrode level) CD variations can contribute greatly to the operating frequency. Etch selectivity to different films is also essential, since resist material is occasionally inadequate to provide a sufficient mask for features which must be etched. To etch a Si trench, for example, an oxide layer must be defined as a mask for the Si, since the presence of organics during trench etching can degrade process performance. In addition to these requirements, there are other levels where very high selectivity to the underlayer is required, for example, to avoid shorting from one conducting metallization level to another. These selectivities are especially important in ULSI circuits, because in such circuits functional levels are overlapped, thus saving valuable space.

The etching processes are generally segmented by material type and function. Most common material classifications include oxide, polysilicon, metal, and certain specialized resist applications. Different functions include a direct lithographic transfer into the underlying substrate, as well as isotropic planarization applications. In recent years, increasing interest in isotropic etching by chemical downstream etching has emerged as an alternative to wet etching. To create a trench capacitor structure, more than 20 different etching steps are required, utilizing a variety of distinct reactors. These delineations are required to maintain process control for critical levels, such as those for the gate electrode. They also are driven by the different chemical systems required to etch the various materials used.

Plasma Etching Development

Because of the fast pace of increasing chip density and the huge cost of developing higher-resolution lithography tools and resists, 248-nm lithographic tools are now being used to expose sub-0.2-mu m features, even though the wavelength of the exposure is greater than that of the printed line width. Since image quality is a function of both focus and exposure dose, such resolutions are obtained, in part, by minimizing the resist thickness and limiting the interference from underlying features. This reduction in resist thickness places limitations on the amount of material which can be removed during the etching. Also, since new resist formulations are required to improve the sensitivity to exposure dose, quite often resist selectivity is reduced. The most sensitive deep-UV resists etch, in some cases, 20% faster than conventional resists.

Most of the films requiring patterning can create interference effects that narrow the lithographic process window. One of the most popular means of minimizing these effects is by using organic or dielectric antireflective coatings, or ARCs. The use of ARCs has found increasing importance as device geometries shrink. In the move from 0.35-mu m-dimension to 0.18-mu m-dimension ground rules, the number of levels requiring ARC has increased by 60%. Typically, for a given exposure tool, the ARC thickness is fixed by the lithographic process. Because the chemical systems used to etch the ARC layer also etch resist, erosion of the resist occurs during the opening of the ARC layer. Additionally, as device dimensions are reduced, design requirements dictate that the required etch depth must remain unchanged or increase. This combination of reduced resist thickness, reduced etch resistance, and static or increasing feature depth requires continuing modification of the etching process.